Handouts

Administrative Handouts

• Student Information Sheet – please fill out this form, attach a recent recognizable photograph, and turn it in Wednesday, January 23rd.
• Class Auditor Permit – follow the instructions on this form if you want to officially audit the class

Papers

This section lists the papers referenced in class. Some links may require you to login using your UT EID if accessed off-campus.

• First Lecture

  • Maurice V. Wilkes. “The Best Way to Design an Automated Calculating Machine,” Manchester University Computer Inaugural Conf., 1951.

    This paper is reproduced in the following books available from the UT library:

    • Earl E. Swartzlander, Jr. Computer Design Development: Principal Papers, Rochelle Park, N.J. : Hayden Book Co., 1976
    • M.R. Williams and Martin Campbell-Kelly. The Early British Computer Conferences. Cambridge, Mass. : MIT Press, 1989.
  • Yale N. Patt. Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE, vol. 89, no. 11, 2001.

• Simultaneous Multithreading

  • Burton Smith. “Architecture and applications of the HEP multiprocessor computer system,” Proc. SPIE, vol. 298 Real-Time Signal Processing IV, 1981, pp. 241-248.
  • Mario Nemirovsky, Forrest Brewer, Roger C. Wood. DISC: Dynamic Instruction Stream Computer. MICRO'91, 1991.
  • D.M. Tullsen, S.J. Eggers, H.M. Levy. Simultaneous Multithreading: Maximizing On-Chip Parallelism. Proceedings of ISCA-22, June 1995.
  • Robert S. Chappell, et. al. Simultaneous subordinate microthreading (SSMT). ISCA 26, 1999.

• Out-of-Order and Superscalar

  • Joseph A. Fisher. Very Long Instruction Word architectures and the ELI-512. ISCA 10, 1983.
  • James E. Smith, Decoupled Access/Execute Computer. 1984. (revised journal version)
  • Yale Patt, Wen-mei Hwu, and Michael Shebanow. HPS, a new microarchitecture: rationale and introduction. MICRO'85, 1985.
  • Yale Patt, Stephen W. Melvin, Wen-mei Hwu, and Michael Shebanow. Critical issues regarding HPS, a high performance microarchitecture. MICRO'85, 1985.

• Dynamic Instruction Scheduling

  • Subbarao Palacharla, Norman P. Jouppi, J. E. Smith, Complexity-Effective Superscalar Processors. ISCA 24, 1997.
  • Jared Stark, Mary D. Brown, and Yale N. Patt, On Pipelining Dynamic Instruction Scheduling Logic. MICRO'00, 2000.

• Runahead Execution

  • James Dundas and Trevor Mudge. Improving data cache performance by pre-executing instructions under a cache miss. ICS 11, 1997.
  • Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors. HPCA 9, 2003.
  • Onur Mutlu, Hyesoon Kim, and Yale N. Patt. Techniques for Efficient Processing in Runahead Execution Engines. ISCA 32, 2005.
  • Onur Mutlu, Hyesoon Kim, and Yale N. Patt. Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. MICRO'05, 2005.

• Trace Cache

  • Stephen W. Melvin and Yale N. Patt. Performance benefits of large execution atomic units in dynamically scheduled machines. ICS 3, 1989.
  • Alexander Peleg and Uri Weiser. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line. U.S. Patent 5381533, 1994.
  • Daniel H. Friendly, Sanjay J. Patel, and Yale N. Patt. Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. MICRO'97, 1997.
  • Sanjay J. Patel, Marius Evers, and Yale N. Patt. Improving trace cache effectiveness with branch promotion and trace packing. ISCA 25, 1998.
  • Eric Rotenberg, Jim Smith, and Steve Bennett. Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. MICRO'96, 1996.
  • Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and Jim Smith. Trace processors. MICRO'97, 1997.
  • Bryan Black, Bohuslav Rychlik, and John Paul Shenn. The block-based trace cache. ISCA 26, 1999.

• Post-Decode Cache

  • Yale N. Patt, et al. Run-time generation of HPS microinstructions from a VAX instruction stream. MICRO 19, 1986.
  • David R. Ditzel, Hubert R. McLellan, and Alan D. Berenbaum. The hardware architecture of the CRISP microprocessor. ISCA 14, 1987.

• Block-Structured ISA

  • Stephen Melvin and Yale N. Patt. Exploiting Fine-grained Parallelism Through a Combination of Hardware and Software Techniques. ISCA 18, 1991.
  • Eric Sprangle and Yale N. Patt. Facilitating superscalar processing via a combined static/dynamic register renaming scheme. MICRO 27, 1994.
  • Eric Hao, et. al. Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. MICRO 29, 1996.
  • Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, et al. Scaling to the End of Silicon with EDGE Architectures. IEEE Computer, 37 (7), 2004.

• Superblocks and Hyperblocks

  • Pohua P. Chang, Scott A. Mahlke, et al. IMPACT: an architectural framework for multiple-instruction-issue processors. ISCA 18, 1991.
  • Scott Mahlke, et al. Effective compiler support for predicated execution using the hyperblock. MICRO 25, 1992.

• Virtual Machines

  • Wayne T. Wilner. “Design of Burroughs B1700.” AFIPS Conf. Proc., Vol. 41, Part 1, 1972.

• Branch Prediction

  • J.K.F. Lee, Alan J. Smith. Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer Vol. 17, Iss. 1, 1984.
  • Tse-Yu Yeh and Yale Patt. Two-Level Adaptive Training Branch Prediction. MICRO 21, 1991.
  • Shien-Tai Pan, Kimming So, Joseph T. Rahmeh. Improving the accuracy of dynamic branch prediction using branch correlation. ASPLOS-V, 1992.
  • Scott McFarling. Combining Branch Predictors. WRL Technical Note TN-36, DEC, 1993.
  • Eric Sprangle, et. al. The Agree Predictor: A Mechanism For Reducing Negative Branch History Interference. ISCA 24, 1997.
  • Daniel A. Jiménez and Calvin Lin. Dynamic Branch Prediction with Perceptrons.HPCA 7, 2001.
  • Andre Seznec. Analysis of the OGEHL predictor. ISCA 32, 2005.
  • Andre Seznec, Pierre Michaud. A case for (partially) tagged Geometric History Length Branch Prediction. Journal of Instruction Level Parallelism, Feb. 2006.

• Performance Measurement

  • John L. Henning (editor), et. al. SPEC CPU2006 Benchmark Descriptions. Computer Architecture News, Vol. 34, No. 4, 2006.
  • James E. Smith. Characterizing computer performance with a single number. Communications of the ACM, Vol. 38, Iss. 10. 1998.
  • Stephen W. Melvin and Yale N. Patt. The Use of Microcode Instrumentation for Development, Debugging and Tuning of Operating System Kernels. ACM SIGMETRICS, 1988.

• RISC

  • David A. Patterson and David R. Ditzel. The case for the reduced instruction set computer. Computer Architecture News, Vol. 8, Iss. 6, 1980.
  • Douglas W. Clark and William D. Strecker. Comments on “the case for the reduced instruction set computer,” by Patterson and Ditzel. Computer Architecture News, Vol. 8, Iss. 6, 1980.

• Cache Coherence

  • James R. Goodman. Using cache memory to reduce processor-memory traffic. ISCA 10, 1983.
  • Mark S. Papamarcos and Janak H. Patel. A low-overhead coherence solution for multiprocessors with private cache memories. Computer Architecture News, Vol. 12, Iss. 3, 1984.
  • Larry Rudolph and Zary Segall. Dynamic decentralized cache schemes for mimd parallel processors. Computer Architecture News, Vol. 12, Iss. 3, 1984.
  • R. H. Katz et al. Implementing a cache consistency protocol. ISCA 12, 1985.
  • E. M. McCreight. “The Dragon Computer System: An. Early Overview.” Proceedings of the NATO Advanced Study Institute on Microarchitecture of VLSI Computers, 1984.

• Parallel Computers

  • Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, et al. Scaling to the End of Silicon with EDGE Architectures. IEEE Computer, 37 (7), 2004.
  • Michael Beford Taylor et al. The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. MICRO 02, 2002.
  • Steve Swanson et al. WaveScalar. MICRO 03, 2003.
  • W. Daniel Hillis. The connection machine. 1985.
  • B. A. Kahle and W. D. Hillis. The Connection Machine model CM-1 architecture. IEEE Trans. on Systems, Man and Cybernetics. 1989.
  • D. E. Shaw. “NON-VON: A Parallel Machine Architecture for Knowledge Based Information Processing.” Proc. of the Seventh International Joint Conf. on Artificial Intelligence, 1981.
  • Robert A. Wagner. The Boolean Vector Machine (BVM). ISCA 10, 1983.

• Consistency Models

  • Leslie Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Trans. on Computers, 1979.
  • M. Dubois, C. Scheurich, and F. Briggs. Memory access buffering in multiprocessors. ISCA 13, 1986.
  • Sarita V. Adve and Mark D. Hill. Implementing Sequential Consistency In Cache-Based Systems. International Conf. on Parallel Processing, 1990.
  • Kourosh Gharachorloo et al. Memory consistency and event ordering in scalable shared-memory multiprocessors. ISCA 17, 1990.

Books

• Frederick P. Brooks, Jr. The mythical man-month: essays on software engineering. Anniversary ed., 1995.
• Robert P. Colwell. The Pentium chronicles: the people, passion, and politics behind Intel's landmark chips. 2006.
• Tracy Kidder. The soul of a new machine. 1981.
• J. E. Thornton. Design of a computer: the Control Data 6600. 1970.
• Glenford J. Myers. Advances in computer architecture, 2nd ed. 1982. – the chapter on capability machines.
• Hank Levy. Capability Based Computer Systems. 1984. – full text online.

x86 ISA

Look for the following x86 manuals (with 64-bit extensions) at Intel's Software Developer's Manuals webpage:

• IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture
• IA-32 Intel Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
• IA-32 Intel Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z
• IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide
• IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide

Alternatively, you may download the older manuals (without 64-bit extensions):

• IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture
• IA-32 Intel Architecture Software Developer's Manual Volume 2: Instruction Set Reference
• IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide

Other

• Project advice from former students