Project Advice

We have asked students who have taken EE 382N before to share their advice on how to approach the project. They came up with these tips:

Form Groups Early

Your ability to work together as a group is very important. If you form groups early, you will be able to:

• start building the basic blocks of your design (caches, memory, adders, shifters, etc.) early on. Knowing the delays and limitations of these structures in advance will help you make better architectural decisions.
• teach each other any useful tools that only one of you knows now.
• work out any differences in working style that could otherwise impede your progress.

Make sure your collaboration does not involve working together on individual assignments!

Learn These Tools

If you are not comfortable with them already, start learning these tools before you actually need to use them:

• Verilog – obviously
• Version control systems such as CVS and SVN make it much easier for multiple people to work on the same project.
• Scripting languages such as Perl allow you to quickly write tools to automate menial tasks (for example, running test cases or generating microcode).
• Build systems such as make and scons help automate project compilation and testing.
• You may use Espresso to generate minimal product-of-sums or sum-of-products implementations of your combinational logic.
• Master the VCS graphical user interface to speed up your debugging. Two very useful features are tracing the drivers of a signal and saving signal configuration.

Verilog Tips

• Make your Verilog code as readable as possible: put code used more than once into reusable modules, use `define statements instead of numbers for constants, and adhere to a naming convention. An example naming convention for the datapath could be:

  (generating_unit)_(signal_name)_(pipeline_stage)[_b if active low]

  Under this convention, if you see a signal named decoder_is_simd_w_b you would know that it is an active low is_simd signal generated in the decoder, corresponding to the instruction in the writeback (w) stage.

• Avoid cluttering your source files with extra modules that can be avoided by using array instantiation or parameters. For example, there's no need to create an xor8 module to implement an 8-bit bitwise XOR; just instantiate the xor2$ gate 8 times:

  xor2$ x[7:0] (parameters);

• You may find these VCS command line options useful (look up how they work by running vcs -help or in the User Manual):

  • +lint=all – generate more warnings (very helpful in avoiding bugs!)
  • -notice – generate more descriptive error and warning messages
  • +incdir, -v, -y – help VCS find your libraries
  • -pvalue, +define – specify parameters to your design (for example, cycle time)
  • +v2k – use new features from the Verilog 2001 standard, such as generate blocks.

  To avoid typing them in each time you run VCS, put all command line options into a file and use vcs -f file.

Other

• If you have accidentally deleted an important file, or even your whole source repository, don't panic! The LRC machines maintain hourly and daily backups for up to a week. The backups for files in any directory are contained in the .snapshot subdirectory within that directory.