Sample simulator runs to help you in debugging your simulator
(Each of the hex files were simulated cycle by cycle using the "run 1"
command and an "idump" was performed after each cycle. *.dump files
show the cycle by cycle output of idump. *.state files summarize the
contents of the pipeline latches. *.timeline shows a timeline of the
execution of the program in the pipeline):
Note that these test cases are not meant to be exhaustive. You should
write your own test cases to make sure that your simulator is working
for every instruction and program.
You can use the following xfig files to show the changes you made to the datapath & state diagram. You can
modify these files using the xfig drawing program installed on LRC UNIX/Linux machines.
Please note that you can submit hand drawn diagrams if you are not comfortable using xfig.
Please generate the timer interrupt only once - at cycle 300.
You can use the following xfig files to show the changes you made to the datapath & state diagram. You can
modify these files using the xfig drawing program installed on LRC UNIX/Linux machines.
Please note that you can submit hand drawn diagrams if you are not comfortable using xfig.