The University of Texas at Austin
Department of Electrical and Computer Engineering

Project Clarifications

EE 382N – Spring 2008
Yale N. Patt, Instructor
Rustam Miftakhutdinov, Aater Suleman, TAs

Default Segment Register Details

As explained in Section 3.7.3.1, Table 3-2 of the Basic Architecture manual, SS, not DS, is the default segment register for memory accesses involving [EBP] + disp8 and [EBP] + disp32 addressing modes, as well as when ESP is used as the base register in the SIB byte (remember, you do not need to implement SIB addressing modes using EBP as the base register).

Interrupt Descriptor Table Details

Make sure that your design uses the Interrupt Descriptor Table entry format described in Section 5.11, Figure 5-2 of the System Programming Guide.