Introduction

The goal of this lab assignment is to extend the LC-3b simulator you wrote in Lab 4 to handle virtual memory. You will augment the existing LC-3b microarchitecture in order to support virtual to physical address translation. You will also provide microarchitectural support for page fault exceptions and change the protection exception from lab #4 to be based on access mode in the PTE.

In Lab 5, the address space of the LC-3b is divided into pages of size 512 bytes. The LC-3b virtual address space has 128 pages, while physical memory has 32 frames. Virtual pages 0-23, which are reserved for the operating system, will be mapped to frames 0-23 and will always be resident in physical memory. Frames 24-31 are available for swapping virtual pages of user programs. There are two modes of operation: supervisor and user. Virtual pages 0-23 cannot be accessed unless the LC-3b is in supervisor mode. Since user programs operate in user mode, they cannot access those pages. Thus the user virtual memory space is 104 pages (pages 24-127).

The input to this new simulator will be:

1. A file entitled ucode5 which holds the expanded microcontrol store.
2. A file holding an LC-3b program that gets loaded into physical frame 8 (x1000). This will be the page table.
3. A file holding an LC-3b user program that gets loaded into virtual page 24 (x3000).
4. A file holding data for the program in page 24. This data will be loaded into virtual page 96 (xC000).
5. A file holding the interrupt/exception vector table that gets loaded into virtual page 1 (x0200). You should form the contents of this table based on the vectors of each interrupt/exception and starting addresses of the service routine for each interrupt/exception.
6. A file holding an LC-3b program that gets loaded into virtual page 9 (x1200). This will be the timer interrupt service routine.
7. A file holding an LC-3b program that gets loaded into virtual page 10 (x1400). This will be the page fault exception handler.
8. A file holding an LC-3b program that gets loaded into virtual page 11 (x1600). This will be the protection exception handler.

New shell code.

A modified shell code has been written for you: lc3bsim5.c

This shell code has the capability of loading the page table into memory. You will need to copy and paste the code you wrote for Lab #4 into this new shell code.

Note that a new command line parameter has been added: the pagetable. To run the simulator, type:

lc3bsim5 <micro_code_file> <page table file> <program_file_1> <program_file_2> ...

The first parameter is the microcode file as before. The second parameter is the page table in LC-3b machine language. Note that since the page table is in physical memory, the first line of this file should have a physical address. For all the program files, (including the interrupt and exception handlers) which are in virtual memory, the first line should have a virtual address.

Specifications

1. Adding support for virtual memory

   The Page Table

   The page table should be placed at the beginning of frame 8 of physical memory. A page table entry (PTE) contains only 9 bits of information, but for convenience, it is represented in a full 16 bit word. Thus one PTE occupies two memory locations. The format of each PTE is as follows:

   PFN = PTE[13:9], the page frame number

   P = PTE[3], the protection bit
   P=0 -> page can only be accessed in supervisor mode
   P=1 -> user has full rights to the page

   V = PTE[2], the valid bit (V=1 for a valid page)

   M = PTE[1], the modified bit (M=1 if page has been written)

   R = PTE[0], the reference bit
   R=1 -> page has been referenced since last timer interrupt
   R=0 -> otherwise

   All other bits are set to zero.

   Page Table Access from the Datapath

   During the execution of instructions, your microcode will have to convert virtual addresses to physical addresses, as well as modify PTEs when necessary. To make address translation possible, we have added more structures to the datapath. We have added these registers: Page Table Base Register (PTBR) and Virtual Address Register (VA). The PTBR points to the first entry of the page table in physical memory and will be initialized by the shell code to the starting address of the page table file you provided as a command line parameter to the simulator. It's used to access a particular PTE during translation. To put the PTBR register onto the bus, you should assert the GatePTBR signal. The VA register is a temporary register to hold the current address being translated. To put the VA register onto the bus and to write to the VA register from the bus, you should assert the GateVA and LD.VA control signals, respectively.

   Translating Addresses

   We will use a simple one-level translation scheme to translate virtual addresses to physical addresses. The high 7 bits of the virtual address (bits[15:9]) specify the page number, and the low 9 bits of the virtual address (bits[8:0]) specify the offset within the page. All 7 bits of the page number will be used during translation. Assume that at the beginning of each address translation phase the virtual address is located in the MAR, and if the operation is a write, a source register holds the data to be written. Address translation consists of the following steps:

   • Save the MAR into the temporary register VA
   
    
   • Load the MAR with the address of the PTE of the page containing the VA.
   MAR[15:8] <- PTBR[15:8]
   MAR[7:0] <- LSHF(VA[15:9], 1)
    
   i.e., MAR <- PTBR + (2 * page_number)
   (Question: Why is the page number multiplied by 2?)
   
    
   • Read the PTE of the page containing the VA into the MDR
   
    
   • Check for a protection exception
   
    
   • Check for a page fault
   
    
   • Set the R bit (reference bit) of the PTE
   
    
   • If the pending access is a write, set the M bit of the PTE
   
    
   • Write the PTE back to memory
   
    
   • Load the physical address into the MAR
   MAR[13:9] <- PFN
   MAR[8:0] <- VA[8:0]
    
   • If the operation is a write, load the MDR with the source register

   To add support for virtual memory, you first need to determine when you need to perform the address translation. Then, you will need to determine how to modify the state diagram so that it supports a "micro-subroutine" written in microcode to translate addresses. You will also need to determine how to return back to the correct state once address translation is complete. For this, you need to augment the microsequencer. You are free to add new control signals, gates, muxes, temporary registers as you wish as long as you fully document your changes.

2. Page Fault Exception

   If the page accessed by a user program is not valid (not in physical memory), then a page fault exception will occur. The exception vector for the page fault exception is x02. You will also write the exception service routine for the page fault. This routine should start at memory location x1400. For the purposes of this assignment, the exception service routine will simply halt the machine. However, don't rely on this. We can test your simulator by replacing your exception routine with our routine which returns from the exception handler using the RTI instruction instead of halting the machine. Upon return from the exception handler, the instruction that caused the exception should be re-executed.

3. Protection Exception

   Protection exceptions occur only when the machine is in user mode, and a memory page whose PTE protection bit is set to 0 is accessed. The memory access that causes a protection exception should not be allowed to complete. The exception vector for the protection exception is x04. The exception handler for the protection exception is located starting at x1600. This routine should halt the machine. However, as with the page fault exception, do not assume that the machine will always be halted after a protection exception occurs.

Writing Code

The user program in page 24 should do the following: calculate the sum of the first 20 bytes stored in memory starting at address xC000 (notice this is on page 96). This sum should then be stored as a 16-bit word at xC014. Then the program should jump to the address pointed to by this sum. Page 96 contains data to be used by the program on page 24. The following numbers should be stored there:
x12, x11, x39, x23, x02, xF6, x12, x23, x56, x89, xBC, xEF, x00, x01, x02, x03, x04, x05, x06, x07.
These should be in the data file for virtual page 96 that you provided as a command line parameter to the simulator and will be loaded into memory when the simulator starts.

The interrupt service routine must traverse the entire page table, clearing the R bits of each PTE. You may assume when writing this code that the start address of the page table is fixed.

The exception handlers you will submit should simply halt the machine.

Initial Page Table Contents

The page table will be initialized upon simulator start-up based on the contents of the page table file you provided as a command line parameter to the simulator. It should look as follows:

Pages 0-23 are in frames 0-23. They are valid and inaccessible by the user.
Page 24 is in frame 25. It is valid and accessible by the user.
Page 96 is in frame 28. It is valid and accessible by the user.
Page 126 is in frame 29. It is valid and accessible by the user. This page contains the user stack.
All other pages are invalid. All invalid PTEs in user space (0x3000-0xFFFF) must be initialized with the protection bit set, i.e. a value of 0x0008. Why?

1. Adequately documented source code of your simulator called lc3bsim5.c.
2. The assembly code for the interrupt service routine, the page table, the interrupt/exception vector table, the page fault exception handler, the protection exception handler, the user program, and the data on page 96, called int.asm, pagetable.asm, vector_table.asm, except_pf.asm, except_prot.asm, add.asm, and data.asm, respectively.
3. The machine code for the interrupt service routine, the page table, the interrupt/exception vector table, the page fault exception handler, the protection exception handler, the user program, and the data on page 96, called int.hex, pagetable.hex, vector_table.hex, except_pf.hex, except_prot.hex, add.hex and data.hex, respectively.
4. The new microcode called ucode5.
5. A file called dumpsim. To generate this file, simulate the LC-3b assembly programs by following the instructions at the end of this section.
6. A text file called readme that explains how you implemented this lab assignment. This readme file should describe the following:
   1. Changes you made to the state diagram. Include a picture similar to the state machine that shows the new states you added (only show your changes or mark your changes in a new state diagram). This picture should include the encodings of new states you added. Clearly show where each state fits in the current state diagram. Describe what happens in each new state.
   2. Changes you made to the datapath. Clearly show the new structures added, along with the control signals controlling those structures. Describe the purpose of each structure.
   3. New control signals you added to each microinstruction. Briefly explain what each control signal is used for.
   4. Changes you made to the microsequencer. Draw a logic diagram of your new microsequencer and describe why you made the changes.

How to generate the dumpsim file

Dump the memory locations containing the page table entries once before the 300th cycle, once after the ISR is done, and finally after the protection exception halts the execution of the program (you should get a protection exception after the jump). Also, dump memory location x3814 (corresponding to which virtual address?) and the current registers after the protection exception.

Things To Consider

The supervisor stack starts at virtual address 0x3000 (SSP is initialized in the shell code). If the user program uses the user stack, the user stack should start at address 0xFE00 (i.e. that user program should initialize R6 to 0xFE00).

1. When do you need to do address translation? How will you return from the address translation to the correct state? An obvious solution would be to have a register which holds the 6-bit return address. Although this is acceptable, think about the possibility of other solutions, e.g. a mechanism that is similar to COND bits in the microsequencer?
2. Since the page table is in physical memory, and the PTBR contains a physical address, the interrupt service routine needs to access the PTEs using physical addresses. An easy way to do this is to turn off virtual to physical address translation when operating in system mode. This will have the added benefit of reducing the number of cycles taken to execute the ISR. What restriction does turning off virtual to physical address translation place on the interrupt service routine code?
3. The microcode used for starting the exception service routine is very similar to the microcode that is used for starting the interrupt service routine. Are there any differences? With these differences in mind perhaps you can combine the states used for interrupt and exception handling.
4. You do not need to worry about nested interrupts for this assignment.
5. If you were unable to finish lab #4 and are hence starting from lab #3, please make a note of this in the readme. You will be unable to simulate the page fault exception, protection exception and timer interrupt if the requirements of lab #4 are not done.