Virtual Memory ============== Pages Frames Resident Access Control 4-levels of access Translation Working Set Balance Set Page Fault Faults vs. Traps Page Table Entry(PTE) Program Region Control Region Valid bit Protection bits Modified bit Reference bit Page replacement Physical Frame Number System Page Table Process Page Table Base Register Length Register VAX Two-level translation PxBR / SBR Page fault latency TLB Context switching Segmentation Cache Memory ============= memory hierarchy Access Latency prefetching post-storing touch instruction spatial locality temporal locality tag store data store dirty bit reference bit hit ratio cache block index bits Tag bits Tag store entry direct mapped cache Set n-way set associative cache fully associative cache byte within block content-addressable memory (CAM) write back / write through replacement algorithms perfect LRU pseudo LRU FIFO Random Victim/Next Victim Tree(Triangle) replacement Instruction/data caches Virtual/physical caches Interprocess communication Cold start problem Runtime Activation Record Context switch Write Back/Write through Virtually indexed physically tagged Write allocate Virtual Space fixation Sector cache Uniprocessor cache consistency Intelligent I/O Direct memory access Inclusion property Interrupt/Exception =================== interrupt exception precise exception fault trap difference between interrupts & exceptions cause when to handle mask context priority polling (interrupt)/ spin-waiting interrupt enable bit Autoincrement architectural state internal state interrupt[exception] vector machine check power failure trace bit sticky flag I/O === asynchronous/synchronous handshaking protocol ethernet polling/interrupt/controller Backdoor Bus DMA (Direct Memory Access) I/O processor Access method of I/O CAM/RAM/ Random access/direct access(DASD)/sequential access Interrupt priority Level I/O structure medium/device/controller transaction transfer/arbitration central/distributive arbitration master/slave Request Grant SACK data/address/control Multiplexing pending bus / split-transaction bus priority arbitration unit daisy chain race condition Aerial Density Rotation Seek Time UniBus Burst Starvation Urgent preempts less urgent Master Synch Slave Synch RAID 0 - 5 Performance/Reliability/Capacity RAID 1: Mirroring RAID 2: ECC RAID 3: Parity and Interleaving RAID 4: Parity with a file per disk RAID 5: Spread parity bits to rotate Processor Speedups ================== SSI MSI LSI VLSI Bit Slice Wafer Fault tolerant computing Triple modulo redundancy Fault avoidance Single point of failure Pipeline Register Fetch Decode Execute Speed up Flow dependency RAW Hazard Vector Processor Scalar Processor Superscalar Super pipelined non-deterministic caches Vector load Vector multiply Instruction buffer Loop buffer Setup time/ Hold time Scoreboard Strip-mining Semantic Gap uOps ROps (AMD) Load Context Instruction (VAX) Vectorizable or Parallelizable Recurrence relation Vector length register Row major order Stride Vector chaining Out-of-order execution Data forwarding Scoreboarding Resource problem Stall Tomasulo's alogorithm Output dependency Register renaming Register alias table Reservation station